Device drivers integrated with the operating system kernel
then make these control and supervision functions available to
higher layers of the stack.
A wide range of programming and configuration support exists
to help developers working with FPGAs. At one end of the
spectrum are tools which map a C++ program almost directly to
an FPGA configuration, aimed at developers with no hardware
skills to tools which enable configuration directly in Hardware
Description Language, (HDL).
Recent developments include a higher-level tool which supports
parallelism, pipelining and streaming and works alongside
the industry-standard OpenCL language. This enables a developer
to separate his algorithm into a control block, written in C
and which runs on a CPU and one or more kernels for acceleration.
The toolset manages the execution of the control block
on the CPU and the kernels on the specified FPGA resources,
removing the need for FPGA expertise and reducing deployment
Tools such as this, including Intel Parallel Studio, greatly
simplify the process of identifying opportunities for acceleration
and implementing them in kernels.
Many application developers will have little interest in acquiring
the level of skill required to interact with FPGA tools and will
look for a higher level of abstraction. From their point of view,
the ideal would be to
have access to a set of
libraries, which would
take care of accelerator
initialisation and FPGA
acceleration of specific
Indeed, some of
this capability is now in
place, with a number
of libraries which cut
already widely used.
These libraries are set
to develop as FPGA
deployment in the cloud
increases and we can
expect the emergence
of specialised libraries,
targeting specific fields,
such as structural or
fluid analyses, physical chemistry or genetics.
Further trends will see even more levels of abstraction for
the user with integration of FPGA acceleration into application
frameworks, for machine learning, data analytics or video coding,
Figure 2. Possible FPGA to data-centre fabric connection routes
Beyond that, turnkey applications will emerge which will
request and apply FPGA acceleration from the data centre
transparently; the end user will be oblivious to the level of effort
which will have gone into libraries but will experience shorter
execution times and/or higher throughput.
Whatever the specifics of the underlying FPGA implementation,
DevOps personnel in the datacentre will require access to the
same debug environment as for any other cloud application.
However, in order to give users the ability to debug their code
at source level, as they are used to, a number of issues must be
addressed for FPGA-accelerated packages.
To carry out steps such as loading of configuration files,
reading and writing of FPGA memory, initialisation of FPGA
logic and starting and stopping execution, FPGA debug
environments need access to the chip’s drivers. This requires
support from the FPGA gasket logic as well as driver code on
the CPU and explicit inclusion of debug structures in the user’s
At this level, there are tools available which provide a level of
FPGA simulation useful to the application developers, allowing
them to conduct high-level debugging in a software-only
Within the cloud data centre many tasks run which have nothing
to do with the execution of user code. Resource availability
tracking, billing support and update deployment are all management
tasks. Orchestration tasks assign computing, network and
storage resources to tasks, whilst at the same time optimising
resource utilisation and task performance. The creation of virtual
machines, their binding to physical resources and their protection
for each other are all functions performed by hypervisors.
FPGA accelerators present
specific challenges to
all three of these functions.
discover the version of
gasket code currently
installed in the FPGA, the
user functions that are
installed and the resources
currently available for
further functions. Open
standard interfaces such
as Intel’s Open Programmable
are available which enable
the management automation
software to gain
access to this information
via the FPGA’s drivers.
Orchestration software needs to know the status of resources
already programmed into the FPGA and those which
remain uncommitted. It also needs to know which of the options
depicted in figure 2 are used to connect the chip to the datacentre
fabric. At the same time, it must have visibility of the
FPGA’s internal memories and must make decisions on whether
to preserve or erase the chip’s configuration.
Hypervisors are also challenged by the heterogeneous characteristics
of FPGAs, as they are used to the uniform fabric of
the data centre.
www.eenewsembedded.com September 2019 Embedded 7 News eeNews Europe