PROCESS
Extreme transistor scaling with 2D materials
ABy Julien Happich t this year’s IEEE International
Electron Devices Meeting, researchers
from imec have presented an
in-depth study of scaled transistors using
MoS2 as a 2D channel, with device performances
outperforming previous 2D-based
FETs.
As a 2D material, MoS2 can be grown in
stable form with nearly atomic thickness
and atomic precision. The researchers synthesized
the material down to a monolayer,
TEM pictures showing (a) 3 monolayers
MoS2 channel, with contact length
13nm and channel length 29nm Transfer
characteristics have improved subthreshold
only 0.6nm thick and then fabricated devices
with scaled contact and channel length,
as small as 13nm and 30nm respectively.
Using these very scaled dimensions, combined with scaled
gate oxide thickness and high K dielectric, the researchers were
able to achieve some of the best device performances so far.
Most importantly, these transistors enable a comprehensive
study of fundamental device properties and calibration of TCAD
models. The calibrated TCAD model is used to propose a realistic
path for performance improvement.
Theoretical studies recommend 2D materials as the perfect
channel material for extreme transistor scaling as only little
short channel effects are expected compared to the current
Si-based devices. Hints of this potential have already been
published with one-of-a-kind transistors built on natural flakes
of 2D materials.
For the first time, imec has tested these
theoretical findings through a comprehensive
set of 2D-materials-based transistor
data. The devices with the smallest footprint
have a channel length of 30nm with a contact
pitch under 50nm.
ON current as high as 250μA/μm has
been demonstrated with a 50nm SiO2 gate
dielectric. Here, an ON current of about 100
μA/μm and an excellent SSmin of 80mV/dec
(for VD =50mV) have been demonstrated
with 4nm HfO2 in a back-gated configuration.
What’s more, device performance is not
swing (SS) with thinner HfO2.
impacted by contact length scaling, confirming that carriers
are injected from the edge of the contact metal directly into the
channel, in line with TCAD simulations. The work confirms that
TCAD models capture large parts of
device physics and guide experimental validation and mapping
the application space. Part of the paper that is presented
at IEDM is dedicated to setting the path for device optimization
for reaching Si-like performance targets.
“Although still an order of magnitude away from Si transistors,
we have brought our MOSFET devices into a realm where
they show promising performance for future logic and memory
applications”, explains Iuliana Radu, director of Exploratory and
Quantum Computing imec.
Greenwaves preps GAP9 IoT processor on FDSOI
By SPeter Clarke tartup Greenwaves Technologies SAS (Grenoble, France)
is developing its second-generation IoT application
processor, the GAP9 and targeting the design at Globalfoundries’
22FDX manufacturing process.
As with the previous generation GAP8,
Greenwaves is targeting applications at
the very edge of the network, such as
machine learning in sensors, and other
battery operated systems. This includes
applications such as people counting,
face identification, dispensing machines.
The previous generation GAP8 is
shipping manufactured in TSMC’s 55nm
manufacturing process. It is an octacore
design based on the RISC-V openssource
GAP9 block diagram.
hardware PULP core developed at the Universities of
Bologna and ETF Zurich. It includes eight such cores plus a
ninth as a controller for a microcontroller section. There is also
a hardware convolution engine (HWCE) to accelerate neural
network operations.
The GAP9 is similar to the GAP8 but is a 9 plus 1 design and
is targeting the 22nm FDSOI process from Globalfoundries. The
ninth RISC-V core is used to calculate memory movements and
scheduling of routines on the main octacore architecture. The
tenth serves as a house-keeping MCU. The use of dynamic
body biasing and architecture enhancements makes GAP9 is
capable of handling problems that are 10 times more complex
than GAP8 with an energy efficiency that is 5 times better than
GAP8.
Improvements include increased internal memory, improved
internal bandwidth and the use of hardware
compression. Martin Croome, vice
president of marketing, said Greenwaves
is targeting clock frequency of 400MHz for
the design although the final specification is
yet to be selected.
GAP9 incorporates additional security
features protecting device makers’ firmware
and models while also protecting devices
from tampering, including hardware support
for AES128/256 cryptography and a
Physical Unclonable Function (PUF) unit
that allows devices to be uniquely and securely identified. GAP9
also includes a CSI2 camera interface with identification applications.
GAP9 extends the capabilities of the GAP8 RI5CY cores with
transprecision floating point units capable of operations on IEEE
16 and 32-bit floats and alternate 16-bit and 8-bit float representations.
This enables simple porting of floating point libraries
and power efficient implementation of algorithms requiring large
dynamic range. GAP9 also supports 4bit data.
Croome said simulation models of the GAP9 have been available
since May 2019 and that development boards containing
GAP9 silicon would ship in the first half of 2020.
www.eenewseurope.com eeNews Europe January 2020 News 19
/
/www.eenewseurope.com