concentrated networks where battery-powered ‘routing nodes’
are nearby to help relay messages. This optimized method for
handling mesh routing functions keeps memory resource needs
relatively low, with less than 160 kB flash and typically 32 kB
of RAM needed. This enables lower-cost silicon and ultimately
more-economical solutions for application developers and
consumers.
The Zigbee Alliance has also specified application profiles,
known as cluster libraries, to simplify the development of
standard products such as light bulbs and occupancy sensors.
The common Zigbee application layer for the IoT is known as
Dotdot, a universal, standard application language for smart
devices to communicate over any network, such as Thread.
Thread
Thread is the most recent wireless technology to emerge for
the IoT, providing IP-based
mesh networking and advanced
security. The Thread Group,
founded in 2014, released the
Thread specification in July 2015
and has continued to enhance it.
Thread is based on a foundation
of existing standards, including
IEEE 802.15.4, and adds special
design specifications for the
network and transport layers.
Like Zigbee, Thread operates in
the 2.4 GHz frequency band and
forms a robust, self-healing mesh
network of up to 250 nodes.
Thread supports low-power, low-cost, mesh scalability, security
Figure 3: Z-Wave is used by more than 700 companies in
more than 2,700 certified interoperable products worldwide.
and native IP addressing. Similar to Zigbee, it offloads some
of the complexity of mesh neighbor processing to static memory
‘lookup tables’, while also keeping the transport/routing
resource needs relatively low to operate on low-cost embedded
devices (with less than 185 kB flash and 32 kB of RAM needed).
Accomplishing this is largely a software effort, which is why
Thread solutions and stack providers take pride in developing
and offering robust solutions to implement on the host silicon,
typically a wireless microcontroller (MCU) or system-on-chip
(SoC) device. As flash memory has become cheaper and integrated
circuits (ICs) have incorporated more memory, the low/
medium memory requirements of Thread stacks have enabled
chip integration of more RF components, such as inductive
matching networks. This frees developers from the complexities
of RF engineering.
Z-Wave
Z-Wave technology is an open, internationally recognized International
Telecommunication Union (ITU) standard (G.9959). It’s
one of the leading wireless smart home technologies available
today, with more than 2,400 certified interoperable products
worldwide. Represented by the Z-Wave Alliance and supported
by more than 700 companies
around the world, Z-Wave is
a key enabler of smart living
solutions for home safety and
security, energy, hospitality, office
and light commercial applications.
Z-Wave technology was
developed in 1999 by Zensys,
a Copenhagen-based start-up,
later acquired by Sigma Designs
in December 2008, and most
recently acquired by Silicon Labs
in April 2018.
One key attraction of Z-Wave is that it provides mesh networking
on sub-GHz frequency bands, avoiding the sometimes
crowded 2.4 GHz industrial, scientific and medical (ISM) band,
which most of the other standards-based IoT protocols use.
Interoperability and backward-compatibility are key tenets
of Z-Wave’s technology philosophy. This outlook has garnered
many fans in the device-manufacturing and ecosystem space,
Intel launches new high-performance FPGA
acceleration card
Intel’s new FPGA Programmable Acceleration Card D5005 will
provide more acceleration capacity for Hewlett Packard Enterprise’s
(HPE) ProLiant DL380 Gen10 server.
The new accelerator is intended to target
computing-intensive markets, such as
streaming analytics, media transcoding,
and network security. The high-performance
Intel FPGA Programmable Acceleration
Card (Intel FPGA PAC) D5005
offers more logic, memory and networking
capability than previous PACs. It has
been qualified in the HPE ProLiant DL380
Gen10 server, providing a higher performance
option than Intel’s earlier PAC built on the Intel Arria 10
GX FPGA.
Intel FPGA PAC D5005 acceleration card is based on an Intel
Stratix 10 SX FPGA. It provides high-performance inline and
lookaside workload acceleration to servers based on Intel Xeon
Scalable processors using the Intel Acceleration Stack.
HPE is the first server OEM to announce pre-qualification of
the Intel FPGA PAC D5005 accelerator card. Other server vendors
are currently qualifying the PAC D5005.
Initial workloads specifically developed for the Intel FPGA PAC
D5005 accelerator card include:
• AI (speech-to-text translation) from Myrtle*
• Network security from Algo-Logic*
• Image transcoding from CTAccel*
• Video transcoding from IBEX*
Compared to the Intel PAC with Intel Arria
10 GX FPGA, Intel FPGA PAC D5005
features more resources, including triple
the amount of programmable logic, up
to 32 GB of DDR4 memory (4x increase)
and faster Ethernet ports (two 100GE
ports versus one 40GE port). With a
smaller physical and power footprint, the Intel PAC with Intel
Arria 10 GX FPGA is intended for a broader range of servers.
Intel
https://buy.hpe.com/b2c/us/en/options/accelerators/
computational-graphics-accelerators-for-servers/computational
graphics-accelerators-for-proliant-servers/intelaccelerators/
p/1010912907
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