DESIGN & PRODUCTS EDGE COMPUTING & AI
network has been rolled out. This will require significant investment
from Telecommunications companies and Governments
alike. These nodes could be smaller edge servers, providing
more than just connectivity.
But how do we ensure performance at the edge? We are, in
fact, seeing a move by the large silicon vendors away from the
scale out model to more of a scale up model, the difference
being rather than buying more servers, we increase the power
within each server. This has a knock-on effect at the edge,
where we now have tremendous processing capability. Another
option (with significantly better green credentials) would be to
reuse older mobiles and/or laptops as lightweight edge nodes,
providing a cheaper deployment option, especially in emerging
markets in Africa and Asia.
Conclusion
Edge computing is going to provide a much easier way for
businesses to quantify and understand what they are investing
in when looking at collecting data, processing it and moving
it. It provides the opportunity to have greater agility and move
towards truly ‘real time’ analytics.
In many ways, the hardware constraints placed on infrastructure
at the Edge is definitely going to give organisations the
onus to have a more in-depth understanding of what data they
need to collect versus what they don’t need to collect, and what
is valuable to their business.
Investing heavily into high cost, high overhead server infrastructure,
with long contracts and a high total cost of ownership
is becoming a thing of the past, especially when little thought is
given to how or when this data could be moved to other infrastructure
such as the cloud.
The current economic climate is forcing businesses to review
how they work and they need to have a flexible business model
to be able to cope with the uncertainty that the future holds.
They need to be able to scale their operation up or down as and
when they need to.
The best way to future proof a business is to collect the data
that is going to give the business the information needed to
move forward, rather than collecting everything under the sun.
How to maximise memory bandwidth
with Vitis and Xilinx UltraScale+ HBM devices
MChris Riley any of today’s workloads and applications such as
artificial intelligence (AI), data analytics, live video
transcoding, and genomic analytics require an increasing
amount of bandwidth. Traditional DDR memory solutions
have not been able to keep up with these growing compute and
memory bandwidth requirements, creating data bottlenecks.
This is visible in figure 1 which illustrates compute capacity
growth vs traditional DDR bandwidth growth.
Fortunately, high-bandwidth memory (HBM) can alleviate
bottlenecks by providing more storage capacity and data
bandwidth using system in package (SiP), memory technology
to stack DRAM chips vertically and using a wide (1024-bit) interface.
For example, the Virtex UltraScale+ HBM enabled devices
(VU+ HBM) close the bandwidth gap with improved bandwidth
capabilities up to 460GB/s delivered by two HBM2 stacks.
These devices also include up to 2.85 million logic cells and up
to 9,024 DSP slices capable of delivering 28.1 peak INT8 TOPs.
In VU+ HBM, there is a hardened AXI Switch that enables access
from any of the 32 AXI channels to any of the HBM pseudo
channels and addressable memory.
This article explores the design aspects that can negatively
impact memory bandwidth, the options available to improve the
bandwidth, and then one way to profile the HBM bandwidth to
illustrate the trade-offs.
These same techniques can be used to profile HBM bandwidth
on the Alveo U280, VCU128, and any Xilinx UltraScale+
HBM device. It can also be used on any accelerated application
using a pre-existing DSA or custom Domain Specific Architectures
(DSAs). We’ll explain the process for creating a custom
DSA in Vivado and how to use Xilinx Vitis unified software
platform to create C/C++ Kernels and memory traffic to profile
the HBM stacks.
Fig. 1: Compute capacity improvements vs DDR bandwidth
improvements.
What can impact memory bandwidth?
Anyone who’s worked with external DRAM interfaces knows
achieving theoretical bandwidth is not possible. In fact, depending
on several different factors, it can be difficult to even come
Chris Riley is Staff Field Applications Engineer at Xilinx –
www.xilinx.com
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