DESIGN & PRODUCTS EDGE COMPUTING & AI
Considering the inherent possibility of reverse engineering
a chip design and the common use of the fabless model in the
industry, it is difficult for any entity to protect their IP without a
patent portfolio, complemented by other forms of protection
such as trade secrets (or ‘know-how’).
A number of market leaders in the chip industry have built
their business model around patent licensing. Notable examples
include Qualcomm and ARM Holdings. Although Qualcomm
derives most of its revenue from chip-making, the bulk of its
profit comes from its patent licensing businesses. Qualcomm’s
licensing business may have suffered over the past two years,
but this was largely due to a dispute with Apple, which has now
been resolved with a one-time settlement of $4.5bn from Apple
to Qualcomm, and a six year licensing deal between the two
companies going forward. ARM goes one step further, generating
practically all its revenue from IP licensing, without ever
selling its own chips. Patent licensing has been very profitable
for Qualcomm and ARM, and it will likely be equally profitable
for companies who build a strong patent portfolio in the AI chips
area. ARM’s business model will present an attractive option for
startups not having the resources to get involved in chip manufacturing,
and the incentive to mitigate risk by remaining fabless
will remain strong even as smaller companies grow.
For startups that may be minded towards being acquired,
there is little doubt that IP is vital for the strongest valuations. It
is unlikely that Intel would have acquired Habana in late 2019
for $2bn if it weren’t for Habana’s patent portfolio stretching
back to 2016, or that Graphcore would have partnered-up with
Microsoft and obtained its current valuation of $1.95bn if they
didn’t have over 60 patent families (groups of patents sharing
the same initial patent filing) to their name.
Investor exit strategies, therefore, continue to dictate the
need for a sound IP strategy.
Another key lesson from related sectors is the very large risk
and reward associated with patent infringement. As recently
as January 2020, Apple and Broadcom were ordered to pay
$1.1bn in damages for infringing Cal Tech patents on Wi-Fi
technology, which the court ruled was used in Broadcom’s wireless
chips. According to Bloomberg, this was the sixth largest
patent-related verdict ever. The need for companies to build
their own patent portfolios for both offensive and defensive purposes
(a ‘defensive’ portfolio implying a threat of a countersuit
thereby protecting from patent suits by competitors), therefore,
remains clear.
Companies are not overlooking IP issues, with records
showing that there are already more than 2,000 patent families
in the field of AI chips. The filing of new patent applications is
increasing rapidly - Intel alone has filed 160 patent applications
for AI chips in the last five years. Existing market leaders as well
as new entrants should, therefore, take note of Intel’s approach
and be mindful not to miss the importance of IP protection for
their inventions, particularly during the early stages.
The legal environment surrounding IP, and in particular patent
law, has changed considerably over the last two decades. It is
also the case that the ever increasing volume of historical patents
and technical publications continues to intensify demands
on both patent offices and patent owners seeking to maintain
patent quality. However, there can be no doubt that IP will
once again prove crucial in this emerging industry. Experienced
technologists and IP practitioners will use lessons from the past
to refine their strategies, and those companies with the right
approach will succeed not just on the merits of their technology
but on leveraging their IP to best advantage.
Channel coding software speeds up edge
networks, reduces latency
AccelerComm announced it has developed a highly optimized
LDPC software decoder in collaboration with Intel. The solution
is integrated into the Intel’s
FlexRAN Reference Software
resulting in increased throughput
by up to 3 times over
alternate implementations, according
to the companies. The
LDPC decoder benefits from a
combination of optimized architectural
and algorithmic enhancements
and use of the powerful Intel Architecture and Intel
Advanced Vector Instructions 512 (Intel AVX512) instruction
sets. The AccelerComm LDPC implementation takes advantage
of these capabilities on Intel Xeon Scalable processor and
with fewer cores delivers performance within 0.1 dB of Intel’s
SDK module. FlexRAN is a reference architecture developed
by Intel to implement virtualised Radio Access Networks which
can be deployed on any part of the wireless infrastructure from
edge to core. The LDPC software decoder can operate as an
upgrade to FlexRAN or standalone and is available directly
from AccelerComm. Channel coding, also known as forward
error correction, is used to correct transmission errors in mobile
communications caused by noise, interference and poor signal
strength.
AccelerComm
www.accelercomm.com
Low-power AI chip features
quantized DNN engine
Socionext announced it has developed a prototype chip that
incorporates newly-developed quantized Deep Neural Network
(DNN) technology, enabling highlyadvanced
AI processing for small and
low-power edge computing devices. The
prototype is part of a research project
on “Updatable and Low Power AI-Edge
LSI Technology Development” commissioned
by the New Energy and Industrial
Technology Development Organization
(NEDO) of Japan. Today’s edge computing devices are based
on conventional, general-purpose GPUs. These processors are
not generally capable of supporting the growing demand for
AI-based processing requirements, such as image recognition
and analysis, which need larger devices at higher cost due to
increases in power consumption and heat generation. In their
place, Socionext has developed a proprietary architecture based
on “quantized DNN technology” for reducing the parameter and
activation bits required for deep learning. The result is improved
performance of AI processing along with lower power consumption.
The architecture incorporates bit reduction including
1-bit (binary) and 2-bit (ternary) in addition to the conventional
8-bit, as well as the company’s original parameter compression
technology, enabling a large amount of computation with fewer
resources and significantly less amounts of data.
Socionext
www.socionext.com
42 News April 2020 @eeNewsEurope www.eenewseurope.com
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