DESIGN & PRODUCTS EDGE COMPUTING & AI
enables Alveo to adapt faster than fixed-function accelerator
card product cycles. Having the flexibility to customise and
reconfigure the hardware gives Alveo a unique advantage over
competition. In the context of this tutorial, we want to customise
and generate several new hardware platforms using different
HBM IP core configurations to profile the impacts on memory
bandwidth to determine which provides the best results.
Fig. 4: How to create a new application project.
There are several ways to build a custom hardware platform but
the quickest is to use Vivado IP Integrator (IPI). Demonstrated
below is one way to do this using Microblaze to generate the
HBM memory traffic in software. This could also be done in
HLS, SDAccel, or in the Vitis tool with hardware accelerated
memory traffic. Using Microblaze as the traffic generator makes
it easy to control the traffic pattern including memory address
locations and we can use a default memory test template to
modify and create loops and various patterns to help profile the
HBM bandwidth effectively.
The steps to build a design in the Vitis tool or SDK are similar
and will include something like this:
1. Open Vivado
File=>Project=>New
1. Create new or open existing Vivado design
1. Target the U280, VCU128 or whichever US+ HBM
device being used
1. Create Block Design
1. Add HBM IP core
Note: Ensure project contains an IP Integrator (IPI) block design
that includes HBM and Microblaze. This block design is what
we refer to as the hardware design and to achieve near maximum
theoretical bandwidth (460GB/s) for both HBM2 stacks
you’ll need to drive continuous traffic to all 16 available Memory
Controllers (MC) via the AXI channels.
Add MicroBlaze, UART and any additional peripheral IP needed.
1. Validate design and generate output products
1. validate_bd_design
2. generate_target all get_files <>.bd
2. Create HDL wrapper for .bd
1. make_wrapper -files get_files <>.bd -top
3. Run synthesis
4. Run Implementation
5. Generate Bitstream
6. Export Hardware
1. File=>Export Hardware
2. If using the Vitis tool you may need to follow these
instructions
1. (If using 2019.2) write_hw_platform -fixed <>/xsa
2. (If using 2019.1) write_dsa -fixed <>.dsa
7. Launch the Vitis tool
8. Select workspace
9. Create new application project and Board Support Package
10. Click Next, Select Create from hardware, click “+” and
point to .xsa
11. Click Next, select CPU Microblaze, Language C
12. Click Next, select “Memory Tests” and click Finish
13. Build and run memory test on target
Conclusion
This article has explained why HBM is needed to keep up with
the growing DDR bandwidth demand and what you can do to
impact DRAM bandwidth, the options available to maximise
your bandwidth, and how to monitor and profile your results.
Using Vitis technology to generate and accelerate HBM traffic
is a quick and easy way to verify your bandwidth requirements
and ensure these are met, whilst also profiling different HBM
configurations to determine which is optimal for your system.
The AI chips race is on – what role will IP play?
By Peter Gray and Szymon Pancewicz In recent years, we have seen the use of artificial intelligence
(AI) and machine learning (ML) expand into a more varied
range of computer and mobile applications. Now, in a similar
fashion to how the spread of low-cost graphics processing units
(GPUs) enabled the deep learning revolution, it is hardware design
(as opposed to algorithms) that is predicted to provide the
foundations for the next big developments. With companies –
from large corporates to startups and SMEs – vying to establish
the fundamental AI accelerator technology that will support
the AI ecosystem, the protection of intangible assets, including
intellectual property (IP), will come to the forefront as one of the
key aspects for success in this sector.
A huge increase in the size of ML models (roughly doubling
about every 3.5 months) has been one of the key driving forces
in the growth of ML model accuracy over recent years. In order
to maintain this almost Moore’s-law growth in complexity, there
is a clear demand in the market for new types of AI accelerators
that can support more advanced ML models, for both training
and inference.
One area of AI that would particularly benefit from new AI
chips is AI inference at the edge. This relatively recent trend of
running AI inference on a device itself, rather than on a remote
Partner Peter Gray and Technical Assistant Szymon Pancewicz
work at Intellectual Property Firm, Mathys & Squire -
www.mathys-squire.com
40 News April 2020 @eeNewsEurope www.eenewseurope.com
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